Published Japanese patent application Kokai JP-A-62-152174 discloses a method of manufacturing an insulated-gate thin-film transistor comprising a semiconductor film which provides a transistor channel adjacent to an insulated gate between source and drain of the transistor. In this known method the semiconductor film is of amorphous silicon. The source and drain are formed from a conductive layer (of ITO, i.e. indium-tin-oxide, in this known method) which is removed from over the gate using a photolithographic step in which the gate serves as a photomask. This step involves exposing a negative photoresist on the conductive layer by illumination through a transparent substrate which is of glass in the known method.
In this known method of JP-A-62-152174, the insulated gate is formed on the substrate, after which the following sequence of layers are deposited: the semiconductor film, the conductive layer and the negative photoresist. The combination of the substrate, semiconductor film and conductive layer together is transparent to the illumination used to expose the photoresist, while the gate which serves as the photomask is opaque. The photomasked part of the ITO layer is etched away from the semiconductor film over the gate, after developing the photoresist.
By using this photolithographic and etching process as compared with a photolithographic lift-off process, the occurrence of short-circuits between the source and drain can be reduced. This improves the yield of the manufacturing process and enhances the reliability of the product. Furthermore, because the edges of the source and drain are defined using the gate as the photomask, an overlap between the gate and the source and drain is small or even avoided so reducing gate-to-drain and gate-to-source capacitance and hence increasing the speed of the TFT.
Published European patent application EP-A-0 071 244 discloses a variant of such a method in which, after the insulated gate is provided on the substrate, the conductive layer and photoresist are deposited before the semiconductor film. The photolithographic step and the definition of the source and drain are then carried out before depositing the semiconductor film. Subsequently this film is deposited either as polycrystalline or amorphous semiconductor material and provides the TFT channel adjacent to its bottom face. An advantage of polycrystalline material is that it has a higher mobility than amorphous material so increasing the speed of the TFTs, but this fact is not commented on in EP-A-0 071 244.
The present invention is based on a recognition that by adopting a different sequence of processing steps still using the gate as a photomask, even better device characteristics can be obtained in a manufacturing process with good yield and reliability. Thus, the applicants have found that it is advantageous to provide the semiconductor film on the substrate and to form the insulated gate (which is to serve as the photomask) at the upper face of the semiconductor film remote from the substrate. The source and drain conductive layer is removed from over the gate, but in this case the transistor channel is adjacent to the upper face of the semiconductor film. This configuration is beneficial especially (but not solely) when providing polycrystalline semiconductor material for high-speed transistors, for example by a crystallizing anneal of the deposited film.
In accordance with the present invention, there is provided a method of manufacturing an insulated-gate thin-film transistor comprising a semiconductor film which provides a transistor channel adjacent to an insulated gate between source and drain of the transistor. The source and drain are formed from a conductive layer which is removed from over the gate using a photolithographic step, in which step the gate serves as a photomask while exposing a negative photoresist on the conductive layer by illumination through a transparent substrate. According to the present invention, such a method is characterised by the steps of:
(a) depositing material for the semiconductor film, on the substrate,
(b) forming the insulated gate at the upper face of the semiconductor film, which face is remote from the substrate,
(c) depositing the conductive layer on the insulated gate and on the semiconductor film beside the insulated gate,
(d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor film and conductive layer which together are transparent to the illumination, and
(e) removing the conductive layer from over the gate so as to leave separate parts of the conductive layer on the semiconductor film at opposite sides of the insulated gate, for forming the source and drain of the transistor.
Thus, by providing the gate as a photomask at the upper face of the semiconductor film, the present invention permits the achievement of low gate-to-drain and gate-to-source capacitances while also obtaining benefits of providing the transistor channel in the semiconductor material remote from the substrate. The applicants find that a better quality channel can be formed adjacent to the upper face of the semiconductor film, as compared with a transistor channel formed at the lower face of a semiconductor film deposited on an insulated gate on the substrate. The properties of the semiconductor material at the upper face are less affected by the substrate. The transistor may comprise an amorphous semiconductor film, but the invention is particularly advantageous for transistors with crystalline film material at least in the region of the transistor channel. Thus, the invention permits the manufacture of high-speed TFTs due both to the low gate-to-drain and gate-to-source capacitances and to the high mobility of the crystalline semiconductor material adjacent to the insulated gate at the upper face of the film.
There is at present considerable interest in developing high-speed polycrystalline TFTs for large-area flat-panel LCDs. These displays are addressed by a matrix of active devices (TFTs or diodes) with at least one device per pixel. The dominant and most widely used technology at present is based on amorphous silicon TFTs. However amorphous silicon TFTs are too slow to provide the driving circuitry so that at present the display is normally connected externally to peripherally-mounted integrated-circuits formed in monocrystalline silicon. The present invention permits the manufacture of sufficiently fast TFTs to implement the scanning and addressing circuitry functions for such large-area displays, and the display can be fabricated on the same substrate as these TFTs. For this purpose, the TFTs should have a sufficiently high mobility and low parasitic capacitance as to allow the construction of row and column shift registers operating at, for example, about 30 kHz and 11 MHz respectively, and for output driver TFTs to be able to charge the appropriate row or column capacitances. Such TFTs can be manufactured in accordance with the invention.
The semiconductor film may be deposited as crystalline material on the substrate in step (a). Thus, for example, by chemical vapour deposition at substrate temperatures of 600.degree. to 620.degree. C., columnar polycrystalline silicon can be deposited in a fine grain form with grain widths of up to about 0.1 .mu.m. TFTs made from this material with the insulated gate at the upper face remote from the substrate may have mobilities in the range of, for example, 5 to 10 cm.sup.2.V.sup.-1.s.sup.-1. It is found that the crystalline grain structure of the upper deposited material is usually better than that deposited immediately adjacent to the substrate.
However, the material for the semiconductor film may be deposited in a fine-grain or even amorphous form in step (a), and this deposited material may then be annealed on the substrate before step (b) so as to crystallize the film at least adjacent to its upper face which is remote from the substrate. Thus, for example, substantially amorphous silicon can be deposited with a substrate temperature of about 540.degree. C. and using low-pressure chemical vapour deposition. Alternatively using plasma-enhanced chemical vapour deposition, amorphous silicon material may be deposited at a temperature as low as about 250.degree. C. to 300.degree. C. The film may be annealed by heating in a furnace. Thus, for example, with a furnace temperature of about 600.degree. C., such amorphous silicon material can be converted into large-grain (about 1 .mu.m in width) polycrystalline silicon as a result of random nucleation. Mobilities in the range of, for example 20 to 80 cm.sup.2.V.sup.-1.s.sup.-1 can be obtained.
However, instead of furnace annealing, it can be even more advantageous to anneal the deposited film material by irradiating its upper face with an energy beam, for example a laser beam. Depending on the detailed conditions polycrystalline silicon mobilities in the range of, for example, 10 to 175 cm.sup.2.V.sup.-1.s.sup.-1 can be obtained in this manner. Furthermore, laser annealing permits selective local crystallization of the film so that, for example, polycrystalline silicon driver TFTs can be formed in peripheral areas of a LCD substrate, and a central area of the same substrate may comprise amorphous silicon devices of the LCD.
Visible light from an argon laser or infrared radiation from a CO.sub.2 laser may be used for the annealing step. However, it is preferable to employ ultra-violet radiation from, for example, an excimer laser. An advantage of ultra-violet radiation is its smaller absorption depth so that, for example, the thickness of the film may be larger than the absorption depth of the ultra-violet radiation in the amorphous material. This smaller absorption depth reduces heating of the substrate and of the interface between the substrate and the semiconductor film. The applicants have found that such heating of the substrate can reduce the yield of the manufacturing process by weakening the adhesion of the semiconductor film to the substrate. Hence, it is advantageous in accordance with the invention to provide the insulated gate at the opposite (i.e. upper) face of the film and to do so after annealing the film to form a good quality crystal grain structure adjacent to its upper face. An insulating layer of the insulated-gate structure may be present on the semiconductor film during the annealing. However, it seems at present that a better crystal grain structure may be obtained for the TFT channel when the upper face of the film is not covered with such a layer during the annealing.
In addition to the advantages already described in providing the gate as a photomask at the upper face of the semiconductor film, a particular method in accordance with the present invention also permits the formation of a lower-doped part of the drain to reduce the field at the drain. Thus, for example, one particular method in accordance with the invention may be further characterised in that the conductive layer is of doped semiconductor material having a lower doping level in a lower part of the layer below an upper part of higher conductance, and in that, after removing the conductive layer from over the gate, the upper part is etched away from the lower part at an area at least at the drain side of the gate so as to space the higher-conductance upper part of the drain laterally from the channel by a lower-doped part of the conductive layer. The provision of this lower-doped part can serve to reduce a localised high electric field which occurs at the drain edge of the gate with high drain bias and which may otherwise lead to degradation of the TFT performance by trapping hot carriers injected into the insulated-gate structure. If desired, a similar low-doped source part may be formed at the source side of the gate. However, using a particular method in accordance with the invention, it is possible to expose the low-doped part only at the drain side and even to define the lateral extent of the low-doped drain part using a shadow-masking effect of the insulated gate.
Thus, for example, in one form in accordance with the invention a second photolithographic step using negative photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the negative photoresist in the second photolithographic step being exposed by illumination through the substrate at such an angle that the insulated gate shadow-masks the photoresist over an area of the conductive layer at the drain side of the insulated gate. In another form in accordance with the invention a photolithographic step using a positive photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the positive photoresist being exposed by illuminating its upper face which is remote from the substrate at such an angle that the insulated gate shadow-masks the photoresist over the area of the conductive layer at the drain side of the insulated gate; and in this case the shadow-masked area of the photoresist which remains after developing the exposed photoresist may be used in a lift-off process to form a complementary mask on the surrounding area for protecting the surrounding area while etching away said upper part of the conductive layer at the drain side of the insulated gate.